Articles

The complexity of manufacturing photolithography has increased significantly. The increase in the level of integration has driven smaller feature-sized integrated circuits (ICs). The evolution in stepper technologies has been geometric. This has enabled the printing of printed ICs with a 45 nm feature size. Improvement in lithographic technology is moving towards 32 nm. This feature-size roadmap poses many challenges to semiconductor manufacturing technology. Advanced photomask synthesis, high-NA steppers, and computational lithography are some examples of the solution space. Optical proximity correction (OPC) and model-based optical proximity correction (MBOPC) are subsets of this solution space. OPC has matured significantly and is the de facto solution for manufacturing photomasks up to the 65 nm node. The OPC technique has been further refined as model-based OPC and has been applied to advanced printing technology of 45 nm. The OPC solution for 45 nm technology has limitations of mask rule check (MRC) and manufacturability restrictions. These restrictions are inevitable in OPC and MBOPC solutions because of the limits in lithographic technology. The technology evolution towards 32 nm has equally challenged the non-linear treatment of wafer-level problems in OPC solutions. PBOPC has limitations in reducing the wafer optical proximity error of the granny's issue, edge placement, mask rule check, etc. PBOPC also has limitations in reducing the mask error enhancement factor. With all these challenges, it is still a formidable solution methodology to address the wafer and mask level issues. Such a formidable solution architecture can result in a limited number of PBOPC solutions. This text looks at the performance of advanced PBOPC features on exposure tuning and the effects of higher-order wafer and aerial image effects. This text also discusses the performance of continuous process correction of masks, lenses, and scanners.